In 2012, we have released an “educational KIT” version of Scanalogic-2. One of the main objectives of this KIT is to show in a fun way how a logic analyzer works. When building/mounting a SCANALOGIC-2 EDU KIT, you will notice that there are 6 distinct blocks. Each one of those blocks is described below
Power supply block
Provides stable and filtered 3.6V for the SRAM (memory) ICs and for the buffer ICs.
USB signal conditioning block
Allows the matching between the USB signal levels and the micro controller’s 5V signals.
Clock Block
Provides a 20MHz clock for the operation of the micro controller and for the signal sampling. This clock is stable to +/- 50 PPM (Pulse Per Minute). The stability of this clock is very important as the precision of the whole logic analyzer depends on it.
MCU Block
The Micro controller block is by definition the heart of the device. It received the capture request from the host (PC) application, initializes the SRAM ICs, watches for trigger conditions and records the exact trigger position. It sends the captured samples to the host application for further analysis and visualization.
SRAM Block
The SRAM block holds the sampled data. There are 4 SRAMs and each one is dedicated to one channels: Each byte of data represents 8 consecutive samples, one for each bit. The main idea of the design is to to feed the samples directly into the SRAMs, without passing by the micro controller. This is the only way to achieve the maximum sampling frequency of 20 MHz.
BUFFER Block
This part is – by definition – used to isolate the outside world from the logic analyzer. However, in this design, it is also used to allow interfacing to a variety of logic levels, from 2V to 5V.
